1. Field of the Invention
The present invention generally relates to the field of packaging for semiconductor products and is directed towards PGA (pin grid array) and LGA (land grid array) modules in particular. PGA and LGA modules typically consist of a ceramic or organic package containing an electronic device wired out to the PGA or LGA for the purpose of interconnecting to the next level of packaging.
2. Description of the Related Art
Conventional systems utilize standard techniques for manufacturing electronic device packages involving the use of pin grid arrays or land grid arrays. PGA or LGA packages provide for easy insertion and removal of the device through a plurality of conductive pins plugged into sockets mounted in the product assembly. An exemplary pin grid array package is shown in FIGS. 1A and 1B. More specifically, FIGS. 1A and 1B illustrate an array of pins/pads 10 formed on a device 11.
The pins/pads 10 in this array are typically nickel and/or gold plated to provide the desired electrical and mechanical characteristics including resistance to wear and corrosion, conductivity and solderability. Plating of these pins/pads 10 is typically done through electroplating which requires that an electrical contact be made to each of the pins 10 during the plating process.
Alternatively, the pads/pins 10 can be heavy gold plated with an electroless process, which requires that the pins 10 be placed in an electroless bath for an extended period of time (e.g., approximately 45 minutes to an hour depending on gold thickness). However, electroplating is more preferable because the electroplating process requires less time in the bath (e.g., approximately 10-12 minutes for the same gold thickness) and results in a more uniform plating.
In the electroplating process, the electrical contact spot generally will not be plated. Therefore, the contact with the pin 10 must be made in a xe2x80x9csafexe2x80x9d area on the pin 10 and be kept as small as possible. xe2x80x9cSafexe2x80x9d areas are areas where missing plating will not produce manufacturing defects. However, there are no truly xe2x80x9csafexe2x80x9d areas for LGA products and, therefore, electroplating is not commonly used with LGA products.
In addition, the plating bath must be kept in constant motion such that local concentration of the bath does not see excessive change due to plate-out depletion. This requires an unimpeded flow of plating chemical around the pins 10 to be plated. Conventional contacts with the pin 10 can sometimes impede the flow of plating chemical.
One conventional electroplating system connects all input/output pins 10 to a common bus 20 at the edge of the package using leads 21, as shown in FIG. 2. After the plating process, the bus 20 is removed. However, this method leaves long leads 21 in the structure. The leads 21 commonly impede the performance of the package, for example, by acting as antennas and causing a high signal to noise ratio and potential xe2x80x9ccross talkxe2x80x9d of signals. Additionally, with ceramic packages it is very costly to removes the bus 20.
Another conventional electroplating system weaves wires between the pins in order to contact them on alternate sides. However, this is a very slow operation and is prone to forming poor contacts and inconsistent alignment to the xe2x80x9csafexe2x80x9d area of the pin. Another conventional system uses a disposable mesh that fits around the pins. The mesh includes multiple contacts that press against the pin shank. However, such mesh structures leave large areas of the pin unplated and can damage pins/plating upon removal.
Also, one conventional electroplating system presses the pins into a conductive foil that is backed by a compliant member. However, such a conductive foil system has poor chemical flow as the foil backing is typically a solid face. Other conventional systems weld a conductive plate to the pin tips. However, this system requires extra steps to align and weld the plate and to shear the plate after the plating process has been completed.
These methods can leave marks on the pins and at times can be unreliable, making the electroplating process very costly. Additionally, with electroplating systems that attach a shorting member to the pins, all pins must be straight and must contact shorting media. Further, xe2x80x9cshadowingxe2x80x9d of the pins occurs when the fluid flow is restricted by the shorting media. Shadowing causes excessive usage of nickel and gold. Further, shorting media which comes in contact with the pins can leave a unplated blemish that can oxidize.
The cost associated with such conventional electroplating systems is increased by the number of assemblies which must be reworked. If only one pin out of the entire array is not plated properly, the entire array package must be reworked. Additionally, the costs associated with such a conventional systems is increased because the shorting media is plated along with the pins contributing to an excessive use of the plating material.
The invention described below overcomes the problems associated with conventional electroplating systems.
It is, therefore, an object of the present invention to provide a structure and method for making electrical contact to all pins or I/O (input/output) pads on a PGA (pin grid array) or LGA (land grid array) chip carrier package for the purpose of electroplating. Contrary to conventional structures, the electrical connections to the pins/pads are made by creating an additional ground plane or using an existing ground plane within the device which connects all signal pins (input/output""s) together to ground.
More specifically, a first embodiment of the invention is a pin grid array structure having a plurality of pins connected to a chip carrier package/organic board, a power plane within the chip carrier package/organic board electrically connected to power pins, a ground plane within the chip carrier/organic board, and fuse portions electrically connecting the ground plane and ground and signal pins. The power plane and the ground plane create the cathode electrical charge in the pins during electroplating of the pins. The fuse portions disconnect the signal pins from the ground plane after the electroplating.
The ground plane may be a continuous, planar conductive layer within the chip carrier package or a conductive wire mesh layer within the chip carrier package. The mesh layer includes mesh lines (e.g., fuses) having a cross-sectional area smaller than the cross-sectional area of the fuse portions. Further, the ground plane includes insulation regions electrically isolating the pins from the ground plane.
Another embodiment of the invention is a system for electroplating a connection array having an internal power plane, an internal ground plane and connection points electrically connected to the internal power plane and the internal ground plane. The system includes an array manufacturing unit producing the connection array, an electroplating bath having a support and producing a plated connection array (the support making an electrical connection to the internal power plane and the internal ground plane), and a fusing unit for disconnecting the internal ground plane from signal connection points in the plated connection array.
The connection array includes fuse portions electrically connecting the internal ground plane and ground and signal connection points. The fusing unit blows the fuse portions and disconnects the signal connection points from the internal ground plane.
The fusing unit may include an array of sockets and a current line connected to the ground plane. The signal connection points are disconnected from the internal ground plane by application of current through the ground plane and referencing the signal pin connection points, one at a time.
Another embodiment of the invention is a method of electroplating which: provides a connection array having an internal power plane, an internal ground plane and connection points electrically connected to the internal power plane and the internal ground plane; attaches the internal power plane and the internal ground plane to a cathode to produce a charge in the connection points; submerges the connection points in a material bath; and disconnects the signal connection points from the internal ground plane.
The connection array includes fuse portions electrically connecting the internal ground plane and the connection points and the disconnecting comprises blowing the fuse portions.
The disconnecting includes connecting the ground plane to a current source and completing a circuit from the current source through the ground plane and through individual ones of the signal connection points. More specifically, the disconnecting includes applying a testing unit to the connection array, where the connection array includes the current source and units for completing the circuit individually through each of the signal connection points. The connection points comprise one of pins and pads and the disconnecting includes inserting the connection points into the testing unit.
The invention is an inexpensive system that provides the necessary electrical contact without damaging the chip carrier package, without masking off excessive or protected areas of the I/O pins or I/O pads and without restricting the flow of plating chemicals around the I/O pins or I/O pads.
The invention insures proper electrical contact for the purpose of plating an PGA or LGA product. The invention lends itself to a high volume manufacturing environment by forming a simple and reliable electrical contact for the purpose of plating.
After the pin grid array package is plated, it is then inserted into a socket that applies a given current to the ground plane. Once the current is applied, it is referenced (directed) to a single signal pin or pad through an external contact with the pin. The current causes the line connected to the ground plane to open (e.g., fuse). This process is repeated until all signals are isolated from each other.